A voltage controlled oscillator (VCO) provides a frequency that is adjustable via a control voltage input. With reference to FIG. 1, there is illustrated a diagram of a VCO circuit 10 that is commonly implemented to achieve such adjustability. The voltage controlled oscillator 10 is formed of a variable capacitor (C) 11, or varactor, in parallel with a fixed inductor (L) 13 and an active circuit to generate a negative resistance. The active circuit is formed of two inverters 15 connected in parallel with each other and oriented to permit the flow of current in opposing directions across the varactor 11. Such a circuit type is generally referred to as an LC-VCO 10. LC-VCO 10 has two time varying output voltages, OUTN and OUTP, which are of nearly identical voltage but which are, preferably, 180° out of phase.
LC-VCO circuits are commonly fabricated into integrated circuits for use, among other things, as signal providers, such as clock signals, to high speed serial links.
With reference to FIG. 2, there is illustrated an integrated circuit implementation of an LC VCO using an NCAP 21 as a varactor. An NCAP is a capacitor formed in the n-well of a Field Effect Transistor (FET) to form an accumulation-mode varactor. While illustrated with reference to fabrication in an n-well, an accumulation-mode varactor may be formed in the p-well of an FET to form a PCAP that may be utilized in the same manner as NCAP 21. Each NCAP is formed of a source and drain 25 and a gate 27. The capacitance of the varactor 11 formed of the two NCAPs 21 can be continually and near instantaneously adjusted through the application of a variable control signal 23 applied to the sources and drains 25 of each NCAP 21.
In integrated circuits, it is advantageous to employ differential signals, especially signals that vary in phase by 180°, to provide increased immunity to on-chip noise and signal coupling. With reference to FIG. 3a, there is illustrated an LC-VCO 10 providing differential control of the varactor 11 via a positive voltage control signal VCP and a negative voltage control signal VCN. The idea is extended in FIG. 3b wherein two varactors 11, 11′ are connected in anti-parallel. The connection of the two varactors 11, 11′ in this manner serves to equalize the parasitic capacitance of the circuit. However, such a connection of the varactors 11, 11′ remains sensitive to the common-mode voltage (CMV) of the two control signals VCP and VCN. The CMV is defined to be equal to 0.5×(VCP+VCN) and is set by the output voltage of the previous circuit.
With reference to FIG. 6, there is illustrated a circuit diagram of a LC-VCO 10 and the circuitry which is typically used to control the operation of the LC-VCO 10 known in the art. A phase-locked loop 65 serves to receive the output voltages 17, 17′ from the LC-VCO 10 and to provide control voltages VCP, VCN to the LC-VCO. Phase-locked loop 65 utilizes a comparator 61 for receiving as input the output voltages 17, 17′ from the LC-VCO, comparing the values of the output voltages 17, 17′, and determining an output frequency of the LC-VCO. The comparator 61 outputs a voltage indicative of the output frequency of the LC-VCO which is subsequently communicated to a charge pump 63 via phase-locked loop 65.
More specifically, comparator 61 is typically formed of a chipset or integrated circuit that receives as inputs a reference signal in the form of a clock signal of known frequency (not shown) and the output voltages 17, 17′ of the LC-VCO 10. Comparator 61 outputs a voltage indicative of the difference in frequency between the reference frequency and output voltages 17, 17′.
Charge pump 63 receives the voltage signal from the comparator 61 via phase-locked loop 65 as well as a reference voltage Vref. While illustrated as a static input, Vref is typically formed as part of a feedback loop (not shown) which operates to maintain a constant Vref during the operation of the charge pump 63. Without such a feedback loop, anomalies may arise, such as changes in the operating environment temperature, that can cause Vref to drift in an unwanted fashion.
Vref operates as the CMV of the charge pump 63. Charge pump 63 utilizes the inputs so as to output control voltages, VCP and VCN, selected to adjust the capacitance of the varactors 11 of the LC-VCO 10. In this manner, the charge pump 63 provides an output signal to the LC-VCO 10 which serves to adjust the frequency of the output voltages 17, 17′ of the LC-VCO 10 which in turn provide feedback 65 to the charge pump 63. This feedback loop allows for the constant adjustment of the operation of the LC-VCO to enable the desired output of the LC-VCO 10.
With reference to FIG. 4, there is illustrated a problem that arises from the traditional configuration illustrated in FIG. 6. With reference to FIG. 4a, there is illustrated the variable capacitance, Cvar, of an exemplary NFET varacator as a function of the difference in voltage applied to the gate side and the drain side of an exemplary NFET varactor, (VG minus VD), where VG is the voltage applied to the gate side of the varactor and VD is the voltage applied to the drain side of the varactor. In operation, a PFET varactor may be similarly utilized.
The resulting curve exhibits a maximum slope when (VG−VD) is equal to zero. The curve asymptotically approaches a maximum capacitance, Cmax, as (VG−VD) increases, and asymptotically approaches a minimum capacitance Cmin as (VG−VD) decreases. As a result, when (VG−VD) is approximately equal to zero, small changes in VG will result in relatively large changes of Cvar. In operation, VG is equal to the CMV of the VCO across the cross-coupled inverters 15. VD is equal to the CMV of the charge pump 63. As VG assumes a value different from VD, changes in VG result in relatively smaller changes in Cvar.
With reference to FIG. 4b, there is illustrated a circuit diagram of a representative varactor 11 with two control voltages Vcn and Vcp. As discussed above, Vcn and Vcp, form the CMV of the output of the charge pump which is equal to Vref. With reference to FIG. 4b there are superimposed two capacitance response curves 71, 73. Curve 71 is a plot of capacitance versus Vcn and curve 73 is a plot of capacitance versus Vcp.
In operation, the difference between the CMV of the charge pump and the CMV of the negative-resistance cell, spanning the inverters of the LC-VCO, in the VCO appear as an offset, ΔCM, in the capacitance-vs-voltage characteristic of a combined varactor pair as illustrated in FIG. 4b. In such a scenario, the control voltages, Vcp and Vcn, are displaced to points along response curves 71, 73 closer to the asymptotic portions of each curve 71, 73. As a result, changes in Vcp and Vcn result in relatively small changes to the capacitance of the varactor 11.
Typically, during the design phase of such a circuit, the CMV of the VCO and the CMV of the charge pump are designed to be equal. However, during operation, differences between the two CMVs can arise as a result of thermal fluctuations and the like. This in turn can cause the offset voltage experienced by the varactors, ΔCM, to limit the ability to control the LC-VCO through the adjustment of the differential control signals, Vcn and Vcp.
This attribute of LC-VCO circuits known in the art results in undesirable difficulty in controlling the signal frequency output of the VCO using differential control signals 23.